1. Field of Invention
This invention relates to integrated circuits and more particularly to delay circuits for use within CMOS integrated circuits.
2. Description of Related Art
In integrated circuits there is a need to have a delay circuit to provide signal delays for various functions. Delay circuits can be found in internal clock generation for clock signals in a DRAM and in power supplies internal to semiconductor chips to control the timing of pump voltages. Setup and hold time is an important specification requiring the delay of signals for an asynchronous DRAM in controlling RAS, CAS, address and data and in a synchronous DRAM for producing the various clocks and controlling data and address.
In U.S. Pat. No. 4,707,626 (Inoue) is shown a delay circuit for internal clock generation. This invention uses an RC network with a cross coupled nor gate as a single shot multivibrator. A MOS transistor is used as a resistor so that the resistance can vary with changes in the power supply and the capacitor is across the input of an inverter stage to vary the trip point with threshold voltage.
A power supply internal to an integrated circuit is discussed in U.S. Pat. No. 5,263,000 (Buskirk et al.) and uses an RC network in conjunction with a Schmitt trigger to produce a delay circuit to control a pump gate for supplying regulated power to the drains of flash EEPROM memory cells. Similarly, U.S. Pat. No. 5,511,026 (Cleveland et al.) shows a delay circuit using an RC network in conjunction with a Schmitt trigger for use with pump gates for an internal power supply providing power to the gates of a flash EEPROM memory cells.
In all cases the delay circuits provide only one RC combination for use in any one delay circuit. Thus the delay of the rising and falling transitions of a signal are controlled with the same delay. A wide variation of rising and falling delays and differences in trigger points results in unbalanced signals. This makes it difficult to achieve set up and hold for all cases in the production of a product. A delay circuit with separate delay control of the rising and falling transitions is needed to overcome the wide variations in delay between rising and falling transitions.